This invention relates to buffers, and more particularly, to output buffers that provide a stable output current and a programmable output power level. The term output buffer, as used herein, refers to all circuits that buffer electrical signals including amplifying and non-amplifying circuits or devices.
The use of output buffers to amplify or otherwise buffer electrical signals is well known in the art. Typical output buffers are implemented using bipolar transistors, complementary metal-on-semiconductor (CMOS) transistors, or a combination of each (Bi-CMOS). Most output buffers have an output stage that provides the output power to the output signal. For CMOS technologies, the output stage typically includes a p-type pull-up metal-on-semiconductor (PMOS) transistor coupled in series with an n-type pull-down MOS (NMOS) transistor. The NMOS transistor is coupled to VSS and the PMOS transistor is coupled to VDD. The output signal is typically taken at the interconnection between the PMOS and NMOS transistors.
The size of each of the output transistors helps determine the drive capability of the output stage. Typically, the output transistors are sized to accommodate an expected load, such as "N" unit loads where "N" is an integer greater than zero. Thus, the drive capability of a typical output buffer is optimized for a particular load size. When an output buffer drives a load that is larger than the expected load size, the output transistors tend to conduct insufficient current to meet the output voltage slew rate requirements, making the output buffer impermissibly slow. When the output buffer drives a load that is less than the expected load size, the output transistors tend to conduct excessive current, which reduces the output voltage slew rate, but increases the transient noise on adjacent signal and power lines. These problems are exacerbated when several output buffers are switched at the same time, such as when a bus is switched from a value of FF to 00 or the like.
To help alleviate some of these problems, U.S. Pat. No. 5,632,019 to Masiewicz suggests providing an output buffer that has programmable source/sink characteristics that can be matched to a particular capacitive load. The output buffer of Masiewicz includes a number of unit buffers that are individually enabled by a programmable control block. By enabling only those unit buffers that are necessary to drive a particular load capacitance, the source/sink characteristics of the output buffer may be matched to the particular load size.
A limitation of Masiewicz is that each of the unit buffers include a pull-up transistor and a pull-down transistor coupled in series between VDD and VSS. In this configuration, the source/sink characteristics of each unit buffer are dependent on the supply voltage. This is particularly problematic when the supply voltage is provided by a battery or the like. A limitation of many batteries, especially alkaline batteries, is that the supply voltage tends to degrade over time. Therefore, if a battery is used, the source/sink characteristics of Masiewicz will tend to degrade over time. Even when the supply voltage is not provided by a battery, the source/sink characteristics of Masiewicz may change with variations in the supply voltage.
Another limitation of Masiewicz is that no Electro-Static-Discharge (ESD) protection is provided. ESD is an increasingly significant problem in integrated circuit design. Potentially destructive electrostatic pulses, which are known as ESD events, are often due to various transient sources such as human or machine handling of the integrated circuit chip during processing, assembly and installation. Most ESD events originate at one of the integrated circuit pads. Since output buffers are typically connected to an integrated circuit pad, it would be desirable to provide some sort of ESD protection to the output buffer circuitry.
For a CMOS output buffer, a typical ESD event includes a high voltage pulse to the output pad, resulting in a high discharge current path through one of the PMOS or NMOS transistors to V.sub.dd or V.sub.ss, respectively. For the NMOS transistor, and depending upon the polarity of the ESD voltage pulse supplied to the pad, the discharge path may proceed either via an avalanche breakdown of the drain/channel junction or via the forward biasing of the drain/channel diode. The avalanche breakdown type of discharge path is the most destructive, since it is most likely to result in irreversible damage to the structure of the NMOS transistor. A similar discharge path may exist through the PMOS transistor.
One approach for providing ESD protection to the PMOS and NMOS transistors of an output buffer is disclosed in U.S. Pat. No. 4,990,802 to Smooha. Smooha discloses placing a resistor between the integrated circuit pad and the buffer circuit. This resistor reduces the current that can pass through the output transistors during an ESD event. This helps reduce the electrical stress in the output buffer transistors. A limitation of this approach is that the source/sink current of the output buffer is also reduced. For an output buffer that is required to drive a relatively high current load through the output pad, placing such a resistor in series with the output pad may produce an unacceptable output voltage slew rate. Therefore, many applications, including those requiring fast response times, may not be compatible with such an approach.
One application where fast response times are often required is in RF communications. The use of power amplifiers and other circuits for transmitting RF signals is well known in the art. Power amplifiers have been used in radio transmitters, television transmitters, CB radios, microwave links, satellite communications systems, local RF networks, and other wireless communication applications. Power amplifiers typically include an output buffer stage for driving the RF signal to an antenna or the like.
In some RF applications, the output buffer is connected to a harmonic filter such as a parallel LC resonant tank or the like. One advantage of using a parallel LC resonant tank is that the tank can be tuned to a desired RF carrier frequency to allow desired frequencies to pass while attenuating spurious emissions. Another advantage of using a parallel LC resonant tank, in conjunction with an RF choke to VDD, is that the peak amplitude of the output signal can be increased to about twice the supply voltage. This helps increase the strength of the RF signal at the antenna. Other tank configurations may provide similar results.
For many applications, such as low power applications, the increased output voltage swing caused by the tank may damage the output buffer circuiting. In a typical low power application, the supply voltage is reduced from, for example, 5.0V to 3.0V. While this helps reduce the power consumed by the device, it also tends to reduce the performance of the device. To help regain some of the performance, a special low voltage manufacturing process may be used when fabricating the device. In a low voltage process, such as a 3.0V process, the gate oxide may be made thinner than in a conventional 5.0V process. This tends to increase the speed and sensitivity of the active devices. Other process parameters may also be optimized for increased performance of the device.
A limitation of using a low voltage process is that the resulting devices may be more sensitive to voltage, and may become damaged when exposed to higher voltages. For example, five volts can damage the gate oxide of some low voltage devices, rendering the devices inoperative. For these reasons, an output stage that is manufactured using a low voltage process may not be compatible with the use of a parallel LC resonant tank. As indicated above, a parallel LC resonant tank may increase the voltage swing on the output terminal of the device. This increased voltage swing may damage the gate oxide or other layer in the low voltage device.